Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

M. Dashtbayazi; M. Sabaghi; S. Marjani

doi:doi:10.11648/j.jeee.20150304.15

| Peer-Reviewed

Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

M. Dashtbayazi, M. Sabaghi, S. Marjani

Published in Journal of Electrical and Electronic Engineering (Volume 3, Issue 4)

Received: 15 March 2015 Accepted: 27 April 2015 Published: 13 August 2015

Views: Downloads:

Download PDF

Share This Article

Twitter
Linked In
Facebook

Abstract

A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply

Published in	Journal of Electrical and Electronic Engineering (Volume 3, Issue 4)
DOI	10.11648/j.jeee.20150304.15
Page(s)	93-96
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2015. Published by Science Publishing Group

Keywords

Comparator, Negative Resistance, Optical Communication Systems, Transconductance Boosting, Dual-Rail Differential Input

References

[1]	H. Traf, G. Holmbert and S. Eriksson “Application of switched current technique to algorithmic DA- and AD-converters”, IEEE Intl. Symp. Circuits and Systems ISCAS, pp.1549-1552, June 1991.
[2]	D.G. Nairn and C.A.T. Salama, “Current-mode algorithmic analog-to-digital converters”, IEEE Journal of Solid-State Circuits, vol. 25, pp.997 – 1004, Aug. 2002.
[3]	M. Kijima, K. Ito, K. Kamei and S. Tsukamoto, “A 6b 3GS/s Flash ADC with Background Calibration”, IEEE Custom Integrated Circuits Conference Digest of Technical Papers, pp.283–286, Sept. 2009.
[4]	Y. Nakajima, A. Sakaguchi, T. Ohkido, T. Matsumoto and M. Yotsuyanagi, “A Self-Background Calibrated 6b 2.7GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp.266–267, June 2009.
[5]	V. Peluso, P. Vancorenland, A.M. Marques, M.S.J. Steyaert and W. Sansen, “A 900-mV Low-Power ΣΔ A/D Converter with 77-dB Dynamic Range”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1887 – 1897, Aug. 2002.
[6]	H. Roh, Y. Choi and J. Roh, “A 89-dB DR 457-W 20-kHz Bandwidth Delta-Sigma Modulator with Gain-Boosting OTAs” Analog Integrated Circuits and Signals Processing, vol. 64, pp. 173 – 182, 2010.
[7]	G.M. Yin, F. Op’t Eynde and W. Sansen, “A High-speed CMOS Comparator with 8-b Resolution”, IEEE Journal of Solid-State Circuits, vol. 27, pp. 208 – 211, Aug. 2002.
[8]	L. Yu, J.Y. Zhang, L. Wang and J.G. Lu, “A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications”, 4th international Conference on Biomedical Engineering and Informatics, vol. 1, pp. 576 – 579, Oct. 2011.
[9]	K. Balasubramanian, “A flash ADC with reduced complexity”, IEEE Transactions on Industrial Electronics, vol. 42, pp. 106 – 108, Aug. 2002.
[10]	C.H. Chan, et al, “A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator”, International SoC Des. Conf, pp. 392-395, Nov. 2009.
[11]	Y. Xu, et al, “Offset-Corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis”, IEEE New Circuits Syst. Conf, pp. 277-280, June 2011.
[12]	B.W. Chen, et al, “A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair”, IEEE Asia-Pacific Conf. Circuits Syst., pp. 648-51, Dec. 2010.
[13]	C.C. Liu, et al, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure”, IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, March 2010.
[14]	B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier”, IEEE J. Solid-State Circuits, vol. 39, pp. 1148–1158, June 2004.
[15]	D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl and B. Nauta, “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time”, IEEE ISSCC Digest of Technical Papers, pp. 314-315, Feb. 2007.
[16]	B. Goll and H. Zimmermann, “A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V”, IEEE ISSCC Digest of Technical Papers, pp.328–329, Feb. 2009.

Cite This Article

Plain Text BibTeX RIS

APA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. (2015). Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. Journal of Electrical and Electronic Engineering, 3(4), 93-96. https://doi.org/10.11648/j.jeee.20150304.15

Copy | Download

ACS Style

M. Dashtbayazi; M. Sabaghi; S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J. Electr. Electron. Eng. 2015, 3(4), 93-96. doi: 10.11648/j.jeee.20150304.15

Copy | Download

AMA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J Electr Electron Eng. 2015;3(4):93-96. doi: 10.11648/j.jeee.20150304.15

Copy | Download

@article{10.11648/j.jeee.20150304.15,
  author = {M. Dashtbayazi and M. Sabaghi and S. Marjani},
  title = {Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {4},
  pages = {93-96},
  doi = {10.11648/j.jeee.20150304.15},
  url = {https://doi.org/10.11648/j.jeee.20150304.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150304.15},
  abstract = {A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply},
 year = {2015}
}

Copy | Download

TY  - JOUR
T1  - Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
AU  - M. Dashtbayazi
AU  - M. Sabaghi
AU  - S. Marjani
Y1  - 2015/08/13
PY  - 2015
N1  - https://doi.org/10.11648/j.jeee.20150304.15
DO  - 10.11648/j.jeee.20150304.15
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
SP  - 93
EP  - 96
PB  - Science Publishing Group
SN  - 2329-1605
UR  - https://doi.org/10.11648/j.jeee.20150304.15
AB  - A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
VL  - 3
IS  - 4
ER  -

Copy | Download

Author Information

M. Dashtbayazi

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
M. Sabaghi

Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran
S. Marjani

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

Download PDF

Sections

Plain Text BibTeX RIS

APA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. (2015). Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. Journal of Electrical and Electronic Engineering, 3(4), 93-96. https://doi.org/10.11648/j.jeee.20150304.15

Copy | Download

ACS Style

M. Dashtbayazi; M. Sabaghi; S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J. Electr. Electron. Eng. 2015, 3(4), 93-96. doi: 10.11648/j.jeee.20150304.15

Copy | Download

AMA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J Electr Electron Eng. 2015;3(4):93-96. doi: 10.11648/j.jeee.20150304.15

Copy | Download

@article{10.11648/j.jeee.20150304.15,
  author = {M. Dashtbayazi and M. Sabaghi and S. Marjani},
  title = {Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {4},
  pages = {93-96},
  doi = {10.11648/j.jeee.20150304.15},
  url = {https://doi.org/10.11648/j.jeee.20150304.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150304.15},
  abstract = {A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply},
 year = {2015}
}

Copy | Download

TY  - JOUR
T1  - Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
AU  - M. Dashtbayazi
AU  - M. Sabaghi
AU  - S. Marjani
Y1  - 2015/08/13
PY  - 2015
N1  - https://doi.org/10.11648/j.jeee.20150304.15
DO  - 10.11648/j.jeee.20150304.15
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
SP  - 93
EP  - 96
PB  - Science Publishing Group
SN  - 2329-1605
UR  - https://doi.org/10.11648/j.jeee.20150304.15
AB  - A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
VL  - 3
IS  - 4
ER  -

Copy | Download